基于结构（structure）和功能（function）的电路逻辑分析是 EDA 工具，特别是逻辑综合、逻辑优化和逻辑检查等工具的核心。由于所有的逻辑分析基于布尔代数（Boolean Algebra）的基础理论，绝大部分问题的算法复杂度都是 NP-Complete，所以需要 EDA 工具基于不同的问题和应用提供高效的 heuristic 算法。本题目涉及的算法可以广泛的应用在逻辑等效验证（LEC）、测试向量生成（ATPG），可测试性分析（testability analysis）等 EDA 工具当中，一个高性能、鲁棒性强的算法是保证相关工具能在各种不同应用环境中面对超大规模电路设计能快速获取结果的关键。

Logic analysis based on circuit structure and function is at the core of many EDA tools, especially for logic synthesis, optimization, and verification. Since logic analysis is based on the theory of Boolean Algebra, the algorithmic complexity of most problems is NP-Complete. Therefore, EDA tools need to provide efficient heuristic algorithms tailored to different problems and applications. The algorithms involved in this task can be widely applied in EDA tools such as Logic Equivalence Checking (LEC), Automatic Test Pattern Generation (ATPG), and testability analysis. A high-performance and robust algorithm is key to ensuring that the relevant tools can quickly obtain results in various application environments when dealing with ultra-large-scale circuit designs.

功能安全验证用于测试和验证航空航天、医疗、汽车电子等关键场景中电子系统对系统性和随机故障的抗性。系统性故障通常由设计或制造缺陷引起，通常会在交付前的功能测试和制造测试阶段解决，而随机故障则需要在电路中额外的设计一些安全机制电路应对，这些安全机制的验证可以在部署前通过软件仿真实现。

Functional safety verification tests and verifies the resilience of mission-critical electronic systems for systematic and random faults. Systematic faults arising from design or manufacturing flaws typically are resolved by functional and manufacturing tests before delivery, while random faults require mechanisms that operate throughout the lifetime of a part. Hardware portions of the system, specifically integrated circuits, insert special safety mechanisms (SMs) into the design. The validation of theses SMs could be achieved in advance by software simulation.

混合尺寸摆放（Mixed-Size Placement）是芯片物理设计（Physical Design）环节中的核心步骤之一，需要同时对芯片内不同尺寸的模块，如宏模块（Macro）和标准单元（Standard Cell），进行有效布局，最终目标是优化芯片的性能、功耗、面积（PPA）指标。宏模块和标准单元的位置互相影响，且对整个芯片布局的质量产生关键性影响，从而决定了芯片的最终物理实现质量。本赛题期望参赛者提出一种混合尺寸布局算法，实现PPA指标的优化。

Mixed-Size Placement is one of the key steps in the IC Physical Design (PD). It requires effective placement of modules of different sizes, such as macros and standard cells, within a chip. The ultimate goal of PD is to optimize the chip Performance, Power consumption, and Area (PPA). The placement of macros and standard cells impacts each other and plays a crucial role in the quality of the overall chip layout, thus determining the final quality of the chip's physical implementation.

汉擎解决方案以汉擎底座为基础，实现中国EDA的上下游协同，完成模拟、数字、制造等国产EDA工具解决方案的串联，以及国产计算生态的推广。基于汉擎底座的Pattern Matching算法可以充分利用汉擎底座的能力。

Hanqing solution realizes the upstream and downstream collaboration of China's EDA, completes the series of analog, digital, and manufacturing EDA tool solutions, and promotes the domestic computing ecosystem. The pattern matching based on Hanqing can fully utilize the capabilities of the of Hanqing.

芯片制造工序非常繁杂，要经历掺杂，氧化，光刻、刻蚀等数十上百道工艺程序，涉及化学、物理、机械等各种加工过程，每个环节都可能引入制造缺陷，使晶体管短路或断路进而导致不能正常工作。DFT 设计，就是在满足芯片正常功能的基础上，在芯片设计阶段通过增加电路，提高故障覆盖率，使定位问题点变得更容易，并且降低芯片测试的难度、时间成本和金钱成本。

Chip manufacturing process is very complicated, to go through doping, oxidation, photolithography, etching and so on dozens of hundreds of process procedures, involving chemical, physical, mechanical and other processes, each link may introduce manufacturing defects, so that the transistor short-circuit or circuit and thus lead to not work properly.DFT design, that is, in order to meet the normal function of the chip on the basis of the chip design stage by adding circuitry to increase fault coverage, make it easier to locate the problem point and reduce the difficulty, time cost and money cost of chip testing. DFT design, based on the normal function of the chip, is to add circuits at the chip design stage to increase the fault coverage, make it easier to locate the problem points, and reduce the difficulty, time and money costs of chip testing.

在 RISC-V 物理设计中同时满足高频、低功耗和设计规则收敛是极具挑战的课题。设计者需要充分利用物理设计工具的功能特性，在众多冲突的设计目标中找到优化平衡，并达到最佳综合指标。

Meeting the high frequency, low power consumption, and design rule convergence in RISC-V physical design is a challenge. Designers need to fully leverage the functional capabilities of physical design tools to find an optimal balance among numerous conflicting design objectives, ultimately achieving the best overall result.