Mixed-Size Placement is one of the key steps in the IC Physical Design (PD). It requires effective placement of modules of different sizes, such as macros and standard cells, within a chip. The ultimate goal of PD is to optimize the chip Performance, Power consumption, and Area (PPA). The placement of macros and standard cells impacts each other and plays a crucial role in the quality of the overall chip layout, thus determining the final quality of the chip's physical implementation.

Hanqing solution realizes the upstream and downstream collaboration of China's EDA, completes the series of analog, digital, and manufacturing EDA tool solutions, and promotes the domestic computing ecosystem. The pattern matching based on Hanqing can fully utilize the capabilities of the of Hanqing.

Logic analysis based on circuit structure and function is at the core of many EDA tools, especially for logic synthesis, optimization, and verification. Since logic analysis is based on the theory of Boolean Algebra, the algorithmic complexity of most problems is NP-Complete. Therefore, EDA tools need to provide efficient heuristic algorithms tailored to different problems and applications. The algorithms involved in this task can be widely applied in EDA tools such as Logic Equivalence Checking (LEC), Automatic Test Pattern Generation (ATPG), and testability analysis. A high-performance and robust algorithm is key to ensuring that the relevant tools can quickly obtain results in various application environments when dealing with ultra-large-scale circuit designs.